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| (R) CD22M3494 Data Sheet January 16, 2006 FN2793.7 16 x 8 x 1 BiMOS-E Crosspoint Switch The Intersil CD22M3494 is an array of 128 analog switches capable of handling signals from DC to video. Because of the switch structure, input signals may swing through the total supply voltage range, VDD to VEE. Each of the 128 switches may be addressed via the ADDRESS input to the 7 to 128 line decoder. The state of the addressed switch is established by the signal to the DATA input. A low or zero input will open the switch, while a high logic level or a one will result in closure of the addressed switch when the STROBE input goes high from its normally low state. Any number or combination of connections may be active at one time. Each connection, however, must be made or broken individually in the manner previously described. All switches may be reset by taking the RESET input from a zero state to a one state and then returning it to its normal low state. CS allows crosspoint array to be cascaded for matrix expansion. Features * 128 Analog Switches * Low rON * Guaranteed rON Matching * Analog Signal Input Voltage Equal to the Supply Voltage * Wide Operating Voltage . . . . . . . . . . . . . . . . . . 4V to 15V * Parallel Input Addressing * High Latch Up Current . . . . . . . . . . . . . . . . . . 50mA (Min) * Very Low Crosstalk * Pin and Functionally Compatible with the Following Types: SGS M3494 and Mitel MT8816 * Pb-Free Plus Anneal Available (RoHS Compliant) Applications * PBX Systems * Instrumentation * Analog and Digital Multiplexers * Video Switching Networks Block Diagram CS STROBE 1 7 TO 128 DECODER 128 DATA RESET 1 LEVEL SHIFTERS 128 128 1 VDD AX0 AX1 AX2 AX3 AY0 AY1 AY2 LATCHES 16 X 8 SWITCH ARRAY X0 - X15 VSS VEE Y0 - Y7 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2000, 2005, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. CD22M3494 Ordering Information PART NUMBER CD22M3494E CD22M3494EZ (See Note) CD22M3494MQ* CD22M3494MQZ* (See Note) CD22M3494MQA* CD22M3494MQAZ* (See Note) CD22M3494SQ CD22M3494SQZ (See Note) *Add "96" suffix for tape and reel. **Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing. applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. PART MARKING CD22M3494E CD22M3494EZ CD22M3494MQ CD22M3494MQZ CD22M3494MQA CD22M3494MQAZ CD22M3494SQ CD22M3494SQZ TEMP. RANGE (C) -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 40 Ld PDIP 40 Ld PDIP** (Pb-free) 44 Ld PLCC (Mitel Ld Compatible) 44 Ld PLCC (Mitel Ld Compatible) (Pb-free) 44 Ld PLCC (Mitel Ld Compatible) 44 Ld PLCC (Mitel Ld Compatible) (Pb-free) 44 Ld PLCC (SGS Ld Compatible) 44 Ld PLCC (SGS Ld Compatible) (Pb-free) PACKAGE PKG. DWG. # E40.6 E40.6 N44.65 N44.65 N44.65 N44.65 N44.65 N44.65 Pinouts CD22M3494E (PDIP) TOP VIEW Y3 1 AY2 2 RESET 3 AX3 4 AX0 5 X14 6 X15 7 X6 8 X7 9 X8 10 X9 11 X10 12 X11 13 NC 14 Y7 15 VSS 16 Y6 17 STROBE 18 Y5 19 VEE 20 40 VDD 39 Y2 38 DATA 37 Y1 36 CS 35 Y0 34 NC 33 X0 32 X1 31 X2 30 X3 29 X4 28 X5 27 X12 26 X13 25 AY1 24 AY0 23 AX2 22 AX1 21 Y4 X14 7 X15 8 X6 9 X7 10 X8 11 X9 12 X10 13 X11 14 NC 15 NC 16 Y7 17 39 Y0 38 NC 37 X0 36 X1 35 X2 34 X3 33 X4 32 X5 31 X12 30 X13 29 NC X14 7 X15 8 X6 9 X7 10 X8 11 X9 12 X10 13 X11 14 NC 15 NC 16 V SS 17 18 19 20 21 22 23 24 25 26 27 28 AY0 V EE AY1 Y7 Y6 Y5 Y4 AX1 STROBE AX2 NC 39 CS 38 NC 37 X0 36 X1 35 X2 34 X3 33 X4 32 X5 31 X12 30 X13 29 NC CD22M3494MQ (PLCC) (MITEL LEAD COMPATIBLE) TOP VIEW RESET DATA V DD AX0 AX3 AY2 CD22M3494SQ (PLCC) (SGS LEAD COMPATIBLE) TOP VIEW RESET V DD AY2 AX0 AX3 DATA NC CS NC Y3 Y2 Y1 Y3 Y2 Y1 6 5 4 3 2 1 44 43 42 41 40 6 5 4 3 2 1 44 43 42 41 40 18 19 20 21 22 23 24 25 26 27 28 AY0 V SS V EE AY1 Y6 Y5 Y4 AX1 STROBE AX2 NC 2 FN2793.7 January 16, 2006 Y0 CD22M3494 Absolute Maximum Ratings DC Supply Voltage (VDD) Voltages Referenced to VEE . . . . . . . . . . . . . . . . . . . . -0.5 to 16V DC Supply Voltage (VDD) Voltages Referenced to VSS . . . . . . . . . . . . . . . . . . . . . -0.5, 16V DC Input Diode Current, IIN For VI, Digital < VSS -0.5V or VI, Analog < VEE -0.5V or VI > VDD 0.5V. . . . . . . . . . . . . . . . . . . . 20mA DC Output Diode Current, IOK For VO, Digital < VSS -0.5V or VO, Analog < VEE -0.5V or VO > VDD 0.5V . . . . . . . . . . . . . . . . . . . 20mA DC Transmission Gate Current . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA Power Dissipation Per Package (Po) For TA = -40C to 85C (PDIP). . . . . . . . . . . . . . . . . . . . . .500mW For TA = 60C to 85C Derate Linearly . . . . . . .12mW/C to 200mW For TA = -40C to 85C (PLCC) . . . . . . . . . . . . . . . . . . . . . . .600mW Thermal Information Thermal Resistance (Typical, Note 1) JA (C/W) PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Maximum Junction Temperature Plastic Package . . . . . . . . . . 150C Maximum Storage Temperature Range (TSTG). . . . . -65C to 150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300C (PLCC - Lead Tips Only) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing. applications. Operating Conditions Operating Temperature Range (TA) Package Type E and Q . . . . . . . . . . . . . . . . . . . . . . -40C to 85C Supply Voltage Range For TA = Full Package Temperature Range VSS = 0V, VEE = 0V, VDD . . . . . . . . . . . . . . . . . . . . . . . 4V to 15V DC Input or Output Voltage VI or VO . . . . . . . . . . . . . . . VEE to VDD Digital Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS to VDD CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER STATIC CONTROLS Supply Current TA = -40C to 85C, VDD = 5V, VSS = 0V, VEE = 0V, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS IDD VDD = 5V, Logic Inputs = VDD VDD = 15V, Logic Inputs = VDD 2.4 (Note 2) - - 2 5 0.8 (Note 2) 10 (Note 4) mA mA V V A High-Level Input Voltage Low-Level Input Voltage Input Leakage Current, Digital VIH VIL IIN VDD = 5V Reset = Low (Note 3) - Electrical Specifications PARAMETER STATIC CROSSPOINTS ON Resistance TA = -40C to 85C, VDD = 12V, VSS = 0V, VEE = 0V, Unless Otherwise Specified. SYMBOL TEST CONDITIONS MIN TYP MAX UNITS rON VSS = VEE = 0V, TA = 25C, VIN = VDD/2, VX - VY = 0.2V VDD = 10V VDD = 12V - 40 36 50 45 6 75 65 75 65 10 ON Resistance rON TA = -40C to 85C, VDD = 10V VIN = VDD/2, VX -VY = 0.2V, VDD = 12V VSS = VEE = 0V TA = 25C, VIN = VDD/2, VX - VY = 0.2V, VSS = VEE = 0V, VDD = 12V Difference in ON Resistance Between Any Two Switches rON 3 FN2793.7 January 16, 2006 CD22M3494 Electrical Specifications PARAMETER Difference in ON Resistance Between Any Two Switches OFF-State Leakage Current TA = -40C to 85C, VDD = 12V, VSS = 0V, VEE = 0V, Unless Otherwise Specified. (Continued) SYMBOL rON TEST CONDITIONS TA = -40C to 85C, VIN = VDD/2, VX - VY = 0.2V, VDD = 12V VSS = VEE = 0V, VDD = 12V |VX - VY| = 12V MIN TYP MAX 10 UNITS IL - - 10 (Note 4) A Electrical Specifications PARAMETER DYNAMIC CROSSPOINTS Switch I/O Capacitance Switch Feedthrough Capacitance TA = 25C, VSS = 0V, VEE = 0V, VDD = 14V, CL = 50pF, Unless Otherwise Specified. TEST CONDITIONS MIN TYP MAX UNITS VIN = VDD/2, f = 1MHz VIN = VDD/2, f = 1MHz - 0.3 5 50 0.01 -95 10 5 75 20 30 - pF pF ns MHz % dB MHz kHz mVPEAK Propagation Delay Time (Switch ON) Signal Input to Output, tPHL or tPLH Frequency Response Channel ON f = 20log (VX/VY) = -3dB Total Harmonic, THD Feedthrough Channel OFF Feedthrough = 20log (VX/VY) = FDT Frequency for Signal Crosstalk, fCT Attenuation of: Control Crosstalk DATA-Input, ADDRESS, or STROBE to Output 40dB 110dB CL = 3pF, RL = 75, VIN = 2VP-P VIN = 2VP-P, f = 1kHz VIN = 2VP-P, f = 1kHz VIN = 2VP-P, RL = 75 VIN = 2VP-P, RL = 1k || 10pF Control Input = 3VP-P Square Wave, tR = tF = 10ns RIN = 1K, ROUT = 10k || 10pF - Electrical Specifications PARAMETER DYNAMIC CONTROLS Digital Input Capacitance Propagation Delay Time STROBE to Output Switch Turn-ON Switch Turn-OFF DATA-IN to Output Turn-ON to High Level Turn-ON to Low Level ADDRESS to Output Turn-ON to High Level Turn-OFF to Low Level TA = 25C, VSS = 0V, VEE = 0V, VDD = 14V, RL = 1k || 50pF, Unless Otherwise Specified. SYMBOL TEST CONDITIONS MIN TYP MAX UNITS CIN VIN = 5V, f = 1MHz - 5 - pF tPSN tPSF tPZH tPZL tPAN tPAF - 50 50 100 100 ns ns - 60 70 100 100 ns ns - 70 70 - ns ns 4 FN2793.7 January 16, 2006 CD22M3494 Electrical Specifications PARAMETER Setup Time CS to STROBE DATA-IN to STROBE ADDRESS to STROBE Hold Time STROBE to CS ADDRESS to CS STROBE to DATA-IN STROBE to ADDRESS DATA-IN to CS Pulse Width STROBE RESET RESET Turn-OFF to Output Delay NOTES: 2. Operation of VIH at 2.4V or VIL at 0.8V will result in much higher supply current (IDD) than for logic inputs equal to VDD or VSS respectively. 3. Reset IIH < 20A, Reset = VIH. 4. At 25C Limit is 100nA. tSPW tRPW tPHZ 20 20 70 100 ns ns ns tDH tAH tCH 10 10 20 10 20 ns ns ns ns ns tCS tDS tAS 10 10 10 ns ns ns TA = 25C, VSS = 0V, VEE = 0V, VDD = 14V, RL = 1k || 50pF, Unless Otherwise Specified. (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 5 FN2793.7 January 16, 2006 CD22M3494 Timing Diagram tCS CS 50% tCH 50% ADDRESS 50% 50% tAS STROBE tSPW 50% tAH tPSN tPSF tDS DATA 50% tDH 50% tRPW RESET tPAF tPZL SWITCH OUTPUT tPZH tPAN 90% 10% 50% tPHZ 90% 10% 50% TRUTH TABLE X AXIS X ADDRESS AX3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 AX2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 AX1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 AX0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X SWITCH X0 X1 X2 X3 X4 X5 X12 X13 X6 X7 X8 X9 X10 X11 X14 X15 AY2 0 0 0 0 1 1 1 1 TRUTH TABLE Y AXIS Y ADDRESS AY1 0 0 1 1 0 0 1 1 AY0 0 1 0 1 0 1 0 1 Y SWITCH Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 6 FN2793.7 January 16, 2006 CD22M3494 To make a connection (close switch) between any two points, specify an "X" address, a "Y" address, set "DATA" high, and switch "STROBE" from low to high. To break a connection, follow this same procedure with "DATA" low. Example: DATA AX3 0 1 0 X ADDRESS AX2 0 0 0 AX1 1 0 1 AX0 1 0 1 Y ADDRESS AY2 1 1 1 AY1 0 1 0 AY0 0 1 0 To connect switch X3 to switch Y4: To connect switch X6 to switch Y7: To break connection from X3 to Y4: 1 1 0 Typical Performance Curve 70 rON vs VIN AT -55C, 25C AND 85C 60 ON RESISTANCE () 50 85C 40 25C 30 -40C 20 10 0 VEE = -6V, VSS = 0V, VDD = 6V -8 -6 -4 -2 0 VIN (V) 2 4 6 8 Pin Descriptions 40 LD PDIP PIN NO. 44 LD PLCC PIN NO. MQ SQ DESCRIPTION SYMBOL POWER SUPPLIES VDD VSS VEE ADDRESS AX0 - AX3 AY0 - AY2 CONTROL DATA STROBE 38 18 42 20 DATA Input determines the state of the addressed switch. A high or one will close the switch. A low or zero will open the switch. STROBE Input enables the action defined by the DATA and ADDRESS Inputs. A low or zero results in no action. The ADDRESS Input must be stable before the STROBE Input goes to the active high level. The DATA Input must be stable on the failing edge of the STROBE. MASTER RESET. A high or one on this line opens all switches. 39 CHIP SELECT. Device is selected when CS is at a high level, allows the crosspoint array to be cascaded for matrix expansion. 5, 22, 23 and 4 24, 25 and 2 5, 24, 25 and 4 26, 27 and 2 X Address Lines. These pins select one of the 16 rows of switches. See the Truth Table for the valid addresses. Y Address Lines. These pins select one of the 8 columns of switches. See the Truth Table for the valid addresses. 40 16 20 44 18 22 44 17 22 Positive Supply. Negative Supply (Digital). Negative Supply (Analog). RESET CS 3 36 40 3 7 FN2793.7 January 16, 2006 CD22M3494 Pin Descriptions (Continued) 40 LD PDIP PIN NO. 44 LD PLCC PIN NO. MQ SQ DESCRIPTION SYMBOL INPUTS/OUTPUTS X0 - X5 X6 - X11 X12 - X15 Y0 - Y7 I/O 33-28, 8-13, 27, 26, 6, 7 37-32, 9-14, 31, 30, 7, 8 Analog or Digital Inputs/Outputs. These pins are the rows X0 - X15. 35, 37, 39, 1, 21, 39, 41, 43, 1, 23, 40, 41, 43, 1, 23, Analog or Digital Inputs/Outputs. These pins are the columns Y0 - Y7. 19, 17, 15 21, 19, 17 21, 19, 18 Pinouts CD22M3494E (PDIP) TOP VIEW Y3 1 AY2 2 RESET 3 AX3 4 AX0 5 X14 6 X15 7 X6 8 X7 9 X8 10 X9 11 X10 12 X11 13 NC 14 Y7 15 VSS 16 Y6 17 STROBE 18 Y5 19 VEE 20 40 VDD 39 Y2 38 DATA 37 Y1 36 CS 35 Y0 34 NC 33 X0 32 X1 31 X2 30 X3 29 X4 28 X5 27 X12 26 X13 25 AY1 AY0 AY1 AY0 V SS V EE V EE AX1 AX2 AY1 AX1 STROBE STROBE AX2 X14 7 X15 8 X6 9 X7 10 X8 11 X9 12 X10 13 X11 14 NC 15 NC 16 Y7 17 39 Y0 38 NC 37 X0 36 X1 35 X2 34 X3 33 X4 32 X5 31 X12 30 X13 29 NC X14 7 X15 8 X6 9 X7 10 X8 11 X9 12 X10 13 X11 14 NC 15 NC 16 V SS 17 18 19 20 21 22 23 24 25 26 27 28 Y7 Y6 Y5 Y4 NC 39 CS 38 NC 37 X0 36 X1 35 X2 34 X3 33 X4 32 X5 31 X12 30 X13 29 NC CD22M3494MQ (PLCC) (MITEL LEAD COMPATIBLE) TOP VIEW RESET DATA V DD AX0 AX3 AY2 CD22M3494SQ (PLCC) (SGS LEAD COMPATIBLE) TOP VIEW RESET V DD AX0 AX3 AY2 DATA NC CS NC Y3 Y2 Y1 Y3 Y2 Y1 6 5 4 3 2 1 44 43 42 41 40 6 5 4 3 2 1 44 43 42 41 40 24 AY0 23 AX2 22 AX1 21 Y4 18 19 20 21 22 23 24 25 26 27 28 Y6 Y5 Y4 NC All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 8 FN2793.7 January 16, 2006 Y0 |
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